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US 2018/0019247 A1Published application
Memory cell and memory apparatus
AssigneeSony Corporation
InventorYUKI YANAGISAWA
Life of this patent
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Abstract
A memory cell of the present disclosure includes: anti-fuses that are respectively inserted into a plurality of paths, one ends of the respective plurality of paths being coupled to one another; a resistor that is inserted into one or more of the plurality of paths; and a selection transistor that is turned on to couple a first coupling terminal to the one ends of the respective paths.
Claims20
A memory cell, comprising:
- anti-fuses that are respectively inserted into a plurality of paths, one ends of the respective plurality of paths being coupled to one another;
- a resistor that is inserted into one or more of the plurality of paths;
- and
- a selection transistor that is turned on to couple a first coupling terminal to the one ends of the respective plurality of paths.
1 more element
A memory apparatus, comprising:
- a memory cell;
- and
- a control section that controls the memory cell,
- wherein the memory cell includes
- anti-fuses that are respectively inserted into a plurality of paths, one ends of the respective plurality of paths being coupled to one another,
- a resistor that is inserted into one or more of the plurality of paths, and
- a selection transistor that is turned on to couple a first coupling terminal to the one ends of the respective plurality of paths.
4 more elements
Dependencies are inferred from the claim text.