Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJi-hoon KIM, Won-chul LEE
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Abstract
A semiconductor memory device may include: a substrate having a cell area defined thereon, the cell area including a cell block area and an edge area; a plurality of bottom electrodes, on the substrate, which are in parallel with a top surface of the substrate and a first direction in parallel with a top surface of the substrate, and are arranged along a second direction intersecting the first direction; and a support structure pattern, in a flat plate shape, which connects the bottom electrodes to each other, supports the bottom electrodes onto the substrate, and includes a plurality of open areas, wherein a first profile, which is a horizontal cross-sectional profile in the edge area of the support structure pattern, has a wave shape.
Claims20
A semiconductor memory device, the semiconductor memory device comprising:
- a substrate having a cell area defined thereon, the cell area including a cell block area and an edge area;
- a plurality of bottom electrodes formed on the substrate, wherein the plurality of bottom electrodes are arranged in rows that extend in a first direction parallel with a top surface of the substrate, arranged in columns that extend in a second direction parallel with the top surface of the substrate and perpendicular to the first direction;
- and
- a support structure pattern having a flat plate shape, wherein the support structure pattern connects the bottom electrodes to each other, supports the bottom electrodes on the substrate, and comprises a plurality of open areas,
- wherein a first profile, which is a horizontal cross-sectional profile of the support structure pattern, from a plan view, has a wave shape in the edge area of the support structure pattern.
A semiconductor memory device, the semiconductor memory device comprising:
- a first bottom electrode array which comprises first bottom electrodes separated from each other by a first gap along a first direction on a substrate and separated from each other by a second gap along a second direction perpendicular to the first direction;
- a second bottom electrode array which comprises second bottom electrodes separated from each other by a third gap along a first direction on the substrate and separated from each other by a fourth gap along the second direction between adjacent first bottom electrodes of the first bottom electrode array;
- and
- a support structure pattern on the substrate between the first bottom electrodes and the second bottom electrodes,
- wherein the first bottom electrodes and the second bottom electrodes are misaligned relative to each other with respect to the first direction, and
- wherein horizontal distances along the second direction from the outermost first and second bottom electrodes to an outermost perimeter of the support structure pattern are the same.
A semiconductor memory device, the device comprising:
- a substrate having a cell area defined thereon, the cell area including a cell block area and an edge area extending around a perimeter of the cell block area;
- a first bottom electrode array which comprises first bottom electrodes separated from each other by a first gap along a first direction on the substrate and separated from each other by a second gap along a second direction perpendicular to the first direction;
- a second bottom electrode array which comprises second bottom electrodes separated from each other by a third gap along a first direction on the substrate and separated from each other by a fourth gap along the second direction between adjacent first bottom electrode arrays;
- and
- a support structure pattern in contact with upper sidewalls of the first and second bottom electrodes, which physically connects the first bottom electrodes and the second bottom electrodes, and supports the first and second bottom electrodes on the substrate,
- wherein a first profile, which is a horizontal cross-sectional profile in the edge area of the support structure pattern, has a wave shape comprised of linear segments.
Dependencies are inferred from the claim text.