Fin-type field effect transistor structure and manufacturing method thereof

A fin-type field effect transistor, comprising:

• a substrate having fins and insulators between the fins;
• at least one gate structure, disposed on the fins and on the insulators, wherein the at least one gate structure comprises a high-k dielectric layer, a work function metal material layer and a gate electrode, the work function metal material layer is disposed on the high-k dielectric layer, and the gate electrode is disposed on the work function metal material layer;
• spacers, disposed on opposite sidewalls of the at least one gate structure, wherein the gate electrode, the work function metal material layer and the high-k dielectric layer are in direct contact with inner sidewalls of the spacers;
• a dielectric layer disposed on the substrate, wherein a material of the dielectric layer is different from a material of the spacers, and the gate electrode, the work function metal material layer and the high-k dielectric layer are in direct contact with sidewalls of the dielectric layer;
• and
• source and drain regions, disposed on two opposite sides of the at least one gate structure.

A method for forming a fin-type field effect transistor, comprising:

• providing a substrate with fins and insulators located between the fins;
• forming a high-k dielectric layer and a work function metal material layer sequentially on the insulators and the fins and over the substrate;
• forming a polysilicon layer and a hard mask pattern sequentially on the work function metal material layer and over the substrate;
• forming polysilicon strips by patterning the polysilicon layer using the hard mask pattern as a mask;
• forming work function metal material strips and high-k dielectric strips by patterning the work function metal material layer and the high-k dielectric layer sequentially using the polysilicon strips and the hard mask pattern as masks;
• forming spacers beside the polysilicon strips and beside the high-k dielectric strips and the work function metal material strips and removing the hard mask pattern during forming the spacers;
• forming an inter-dielectric layer over the substrate and abutting the polysilicon strips, the work function metal material strips and high-k dielectric strips after forming the spacers;
• removing the polysilicon strips to form recesses exposing the inter-dielectric layer and the work function metal material strips;
• and
• forming gate structures by forming gate electrode stacks within the recesses and on the work function metal material strips and the high-k dielectric strips.