Method and Structure of Three-Dimensional Chip Stacking
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Wen-Chih Chiou, Yung-Chi Lin
Life of this patent
Estimating the term…
Abstract
A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
Claims20
A package comprising:
- a first device die;
- a second device die over and bonded to the first device die through hybrid bonding;
- an encapsulating material encapsulating the second device die therein;
- and
- an interconnect structure over the second device die, wherein the interconnect structure extends beyond edges of the second device die, and edges of the interconnect structure are co-terminus with respective edges of the first device die.
A package comprising:
- a first device die comprising:
- a first surface dielectric layer;
- and
- a first bond pad in the first surface dielectric layer;
- a second device die over the first device die, the second device die comprising:
- a second surface dielectric layer bonded to the first surface dielectric layer;
- and
- a second bond pad in the second surface dielectric layer, the second bond pad being bonded to the first bond pad;
- a molding compound continuously extending from a top surface of the second device die to a bottom surface of the second device die, with the second device die in the molding compound, wherein the molding compound has a bottom surface contacting, without bonding to, a top surface of the first device die;
- and
- an interconnect structure over the second device die.
A package comprising:
- a first device die;
- a second device die over and bonded to the first device die, wherein a first surface dielectric layer in the first device die is bonded to a second surface dielectric layer in the second device die, and a first surface conductive feature in the first device die is bonded to a second conductive feature in the second device die;
- an encapsulating material encapsulating the second device die therein, and a bottom surface of the encapsulating material contacts a top surface of the first device die;
- a through-via continuously extending from a top surface of the encapsulating material to a bottom surface of the encapsulating material, wherein the through-via is bonded to the first device die;
- and
- an interconnect structure over the second device die, wherein the interconnect structure is electrically coupled to the through-via.
Dependencies are inferred from the claim text.