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US 2018/0019201 A1Published application
Switched power stage with integrated passive components
AssigneeEndura Technologies LLC
InventorTaner Dosluoglu
Life of this patent
Estimating the term…
Abstract
A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.
Claims14
An integrated chip package comprising:
- a flip-chip type integrated circuit (IC) chip including a system-on-chip (SoC) and a switching voltage regulator, the switching voltage regulator including at least a first switch and a second switch coupled in series between a higher voltage level connection and a lower voltage level connection;
- a multi-layer substrate having a cavity with at least one inductor in the cavity, the at least one inductor having a plurality of upper layers of traces interspersed by ferrite material, the inductor including a first end and a second end;
- and
- a plurality of micro-bumps connecting the IC chip to the substrate including a micro-bump connecting a node between the first switch and the second switch to the first end of the inductor.
1 more element
A flip-chip package comprising:
- a flip-chip type integrated circuit (IC) chip including a system-on-chip (SoC) and a multi-phase voltage regulator, the multi-phase voltage regulator including a first pair of transistors coupled in series and a second pair of transistors coupled in series;
- and
- a multi-layer package substrate having a plurality of redistribution layers and a first inductor and a second inductor, the first inductor and the second inductor formed of a plurality of electroplated traces, each of the first and second inductors including a first end and a second end, the plurality of electroplated traces formed of conductive layers within a cavity of the multi-layer package substrate, ferrite material between at least some of the conductive layers, and wherein at least one of the first plurality of electroplated traces is configured to connect the second end of the first inductor to the first end of the second inductor;
- and
- a plurality of bumps configured to connect the IC chip to the multi-layer package substrate at a plurality of nodes including a supply node, a ground node, a load output node, and inductor nodes, the load output node including the connection between the second end of the first inductor and the first end of the second inductor, the inductor nodes including a node configured to connect a node between the first pair of transistors to the first end of the first inductor structure and a node configured to connect a node between the second pair of transistors to the second end of the second inductor structure.
2 more elements
Dependencies are inferred from the claim text.