Wiring substrate and semiconductor package
AssigneeShinko Electric Industries Co., Ltd.
InventorToyoaki SAKAI
Life of this patent
Estimating the term…
Abstract
A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.
Claims15
A wiring substrate comprising:
- an insulating layer;
- and
- a wiring layer buried in the insulating layer at a first surface of the insulating layer,
- the wiring layer including a first portion and a second portion, the first portion being narrower and thinner than the second portion, the first portion including a first surface exposed at the first surface of the insulating layer, the second portion including a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer, the opening being open at a second surface of the insulating layer opposite to the first surface thereof.
A semiconductor package, comprising:
- a wiring substrate,
- the wiring substrate including
- an insulating layer;
- and
- a wiring layer buried in the insulating layer at a first surface of the insulating layer;
- and
- a semiconductor chip mounted over the first surface of the insulating layer,
- wherein the wiring layer includes a first portion and a second portion, the first portion being narrower and thinner than the second portion, the first portion including a first surface exposed at the first surface of the insulating layer, the second portion including a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer, the opening being open at a second surface of the insulating layer opposite to the first surface thereof, and
- wherein the first portion includes a wiring pattern, and the second portion includes a first pad connected to the semiconductor chip, exposed at the first surface of the insulating layer, and a second pad for external connection, exposed in the opening.
Dependencies are inferred from the claim text.