Thermally enhanced semiconductor package having field effect transistors with back-gate feature

Abstract

The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a non-silicon thermal conductive component, a silicon layer with a thickness between 100 Å and 10 μm over the thermal conductive component, a buried oxide (BOX) layer over the silicon layer, an epitaxial layer over the BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the silicon layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Dependencies are inferred from the claim text.