US 2018/0019170 A1 · SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION

Abstract

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Claims22

Dependent claims

An integrated circuit (IC) comprising:

a first fin including strain throughout at least a portion of the first fin, the first fin having a width of less than 30 nanometers, a height of greater than 35 nanometers, and a germanium concentration of greater than 40 atomic percent;
a second fin including one or more of aluminum, gallium, or indium, the second fin also including one or more of nitrogen, phosphorus, arsenic, or antimony;
a first gate structure over the first fin;
a second gate structure over the second fin;
a first source region comprising a p-type impurity and a first drain region comprising a p-type impurity, wherein the first fin is between the first source and drain regions;
and
a second source region comprising an n-type impurity and a second drain region comprising an n-type impurity, wherein the second fin is between the second source and drain regions.

4 more elements

Dependencies are inferred from the claim text.

Self-aligned 3-d epitaxial structures for mos device fabrication

Life of this patent

Self-aligned 3-d epitaxial structures for mos device fabrication

Life of this patent

Abstract

Claims22