Systems and methods for producing flat surfaces in interconnect structures
AssigneeTessera, Inc.
InventorsCyprian UZOH, Vage OGANESIAN, Ilyas MOHAMMED
Life of this patent
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Abstract
In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.
Claims20
1-20. (canceled)
A method for fabricating an apparatus comprising one or more semiconductor devices, the method comprising:
- obtaining a structure comprising a substrate with
- a plurality of openings in a top surface of the substrate, each opening extending at least partially into the substrate and
- a conductive layer covering the substrate and extending into each opening to provide at least a part of an interconnect structure, a surface of the conductive layer having a protrusion over each opening that extends upward from a surrounding adjacent area;
- and
- polishing a surface of the structure until the conductive layer is removed between at least two openings.
A method for fabricating an apparatus comprising one or more semiconductor devices, the method comprising:
- (a) obtaining a substrate comprising a plurality of openings in a top surface of the substrate, each said opening extending at least partially into the substrate;
- (b) forming a conductive layer over the substrate, the conductive layer covering the substrate and extending into each said opening to provide in each said opening at least a part of an interconnect structure in the apparatus, the conductive layer having a recess over each said opening;
- (c) processing the conductive layer, the processing comprising:
- (c1) performing a thermal treatment of at least a part of the conductive layer to change the grain size of at least a part of the conductive layer;
- then
- (c2) polishing the conductive layer at least until the conductive layer has no recesses over the openings but still covers the substrate;
- and then
- (3) further polishing the conductive layer to remove at least a first part of the conductive layer between the openings but leave at least a second part of the conductive layer in each said opening, the second parts not being interconnected by the conductive layer.
Dependencies are inferred from the claim text.