Semiconductor device manufacturing method
AssigneeFuji Electric Co., Ltd.
InventorHideaki MATSUYAMA
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AssigneeFuji Electric Co., Ltd.
InventorHideaki MATSUYAMA
Estimating the term…
There is a problem that even if impurities are made to thermally diffuse in a temperature range of 700° C.-1150° C., a good ohmic contact cannot be formed in a p-type group-III nitride semiconductor layer. Provided is a semiconductor device manufacturing method having a group-III nitride semiconductor substrate and a p-type group-III nitride semiconductor layer on the group-III nitride semiconductor substrate, including forming a magnesium containing layer on and in direct contact with the p-type group-III nitride semiconductor layer; and annealing the p-type group-III nitride semiconductor layer at a temperature more than or equal to 1300° C. to form a p+-type region which contains magnesium as an impurity in the p-type group-III nitride semiconductor layer located immediately below the magnesium containing layer.
A semiconductor device manufacturing method having a group-III nitride semiconductor substrate and a p-type group-III nitride semiconductor layer on the group-III nitride semiconductor substrate, comprising:
Dependencies are inferred from the claim text.