Semiconductor test device and semiconductor test method
AssigneeSK hynix Inc.
InventorMin Sik HAN
Life of this patent
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Abstract
A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.
Claims20
A semiconductor test device comprising:
- a DQ signal receiver configured to receive a first DQ signal through a first DQ pin;
- a test mode register set signal processor configured to receive a test mode register set signal in response to the first DQ signal, and configured to output a test mode register set pulse signal;
- and
- a test mode command generator configured to generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.
A semiconductor test device comprising:
- a DQ signal application circuit configured to apply a first DQ signal through a first DQ pin of a first semiconductor chip;
- an address application circuit configured to apply a first address corresponding to a first test command through an address pin coupled in common to the first semiconductor chip and a second semiconductor chip different from the first semiconductor chip;
- and
- a test result input circuit configured to receive a test result obtained as a result of executing the first test command in the first semiconductor chip.
A semiconductor test method for testing a plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip comprising:
- applying a first DQ signal through a first DQ pin of the first semiconductor chip;
- applying a first address corresponding to a first test command through an address pin coupled in common to the first semiconductor chip and the second semiconductor chip;
- and
- receiving a test result obtained as a result of executing the first test command in the first semiconductor chip.
Dependencies are inferred from the claim text.