Replicating test case data into a cache and cache inhibited memory
AssigneeInternational Business Machines Corporation
InventorsManoj Dusanapudi, Shakti Kapoor
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorsManoj Dusanapudi, Shakti Kapoor
Estimating the term…
Data is replicated into a memory cache and cache inhibited memory in data segments with segment size that provides non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries allows replicated testing of the memory cache and cache inhibited memory while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases generated for cacheable memory to be replicated and used for cache inhibited memory. The processor can then use a single test replicated in this manner by branching back and using the next slice of the replicated test data in the memory cache and cache inhibited memory.
An apparatus for testing a computer processing device comprising:
A computer-implemented method executed by at least one processor for testing a computer processor device comprising:
A computer-implemented method executed by at least one processor for testing a computer processor device comprising:
Dependencies are inferred from the claim text.