Sample-and-Hold Circuit
AssigneeFreescale Semiconductor, Inc.
InventorsAndré Luis VILAS BOAS, Richard Titov Lara SAEZ, Javier Mauricio OLARTE GONZALEZ
Life of this patent
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Abstract
A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.
Claims20
A sample-and-hold circuit comprising:
- a switch enable terminal for receiving a switch enable signal;
- an input terminal for intermittently receiving an input voltage;
- a first transistor having one conducting terminal coupled to the input terminal, having another conducting terminal coupled to a node and having a control terminal coupled to the switch enable terminal;
- an intermediate capacitor coupled between the node and a ground terminal;
- a second transistor having one conducting terminal coupled to the node, having another conducting terminal coupled to an output terminal and having a control terminal coupled to the switch enable terminal;
- and
- a hold capacitor coupled between the output terminal and the ground terminal,
- wherein, when the input terminal is receiving the input voltage, a first value of the switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the intermediate capacitor and the hold capacitor to the sampled input voltage,
- wherein, when the input terminal is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at the output terminal, the sampled input voltage until the hold capacitor discharges, and
- wherein the charge on the intermediate capacitor delays discharging of the hold capacitor.
A power management controller comprising:
- a bandgap buffer configured to intermittently output a reference voltage;
- a sample-and-hold circuit coupled to the bandgap buffer;
- and
- logic configured to output a bandgap buffer enable signal to the bandgap buffer and to output a switch enable signal to the sample-and-hold circuit,
- wherein the sample-and-hold circuit includes:
- a switch enable terminal configured to receive the switch enable signal;
- an input terminal configured to receive the reference voltage;
- a first transistor having one conducting terminal coupled to the input terminal, another conducting terminal coupled to a node and a control terminal coupled to the switch enable terminal;
- an intermediate capacitor coupled between the node and a ground terminal;
- a second transistor having one conducting terminal coupled to the node, another conducting terminal coupled to an output terminal and a control terminal coupled to the switch enable terminal;
- and
- a hold capacitor coupled between the output terminal and the ground terminal,
- wherein, when the input terminal is receiving the reference voltage, a first value of the switch enable signal causes the sample-and-hold circuit to sample the reference voltage and to charge the intermediate capacitor and the hold capacitor to the reference voltage,
- wherein, when the input terminal is not receiving the reference voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at the output terminal, the reference voltage until the hold capacitor discharges,
- wherein the charge on the intermediate capacitor delays discharging of the hold capacitor.
A method with a sample-and-hold circuit having a switch enable terminal coupled to a control terminal of a first transistor, a control terminal of a second transistor and a control terminal of a third transistor, comprising:
- for a first interval, receiving a reference voltage at an input terminal;
- during at least some of the first interval, receiving a first value of a switch enable signal at the switch enable terminal, thereby:
- turning on the first transistor which has one conducting terminal coupled to the input terminal and another conducting terminal coupled to a first node,
- charging a first intermediate capacitor coupled between the first node and ground,
- turning on the second transistor which has one conducting terminal coupled to the first node and another conducting terminal coupled to a second node,
- charging a second intermediate capacitor coupled between the second node and ground,
- turning on the third transistor which has one conducting terminal coupled to the second node and another conducting terminal coupled to an output terminal, and
- charging a hold capacitor coupled between the output terminal and ground;
- and
- during a second interval occurring immediately subsequent to the first interval, cease receiving the reference voltage, and begin receiving a second value of the switch enable signal, thereby:
- turning off the first transistor,
- turning off the second transistor, and
- turning off the third transistor,
- wherein the charge on the second intermediate capacitor delays discharging of the hold capacitor when the input terminal is not receiving the reference voltage.
Dependencies are inferred from the claim text.