CMOS Anti-Fuse Cell
AssigneeNEO Semiconductor, Inc.
InventorFu-Chang Hsu
Life of this patent
Estimating the term…
Abstract
A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
Claims20
A circuit able to perform an anti-fuse function, comprising:
- a first P+ diffusion layer deposited over an N− well substrate and configured to have a first lip extending underneath of a first portion of a first gate oxide;
- a second P+ diffusion layer deposited over the N− well substrate and configured to have a first lip extending underneath of a second portion of the first gate oxide and a second lip extending underneath of a first portion of a second gate oxide;
- a polysilicon select gate (“PSG”) situated over the first gate oxide and configured to receive a voltage;
- and
- a polysilicon control gate (“PCG”) situated over the second gate oxide and able to breakdown at least a part of the first portion of second gate oxide near the second lip of the second P+ diffusion layer when a high voltage is applied to the PCG.
A method for programming an anti-fuse cell in a semiconductor device, comprising:
- maintaining a first voltage at a first drain P+ diffusion layer disposed over an N-well via a contact;
- applying a second voltage to a control gate (“CG”) deposited over at least a portion of the first drain P+ diffusion layer separated by a first gate oxide layer;
- and
- creating a leakage path in the first gate oxide layer adjacent to the first drain P+ diffusion layer when the voltage difference between the first voltage and the second voltage exceeds a voltage threshold of the first gate oxide layer.
A method of fabricating an integrated circuit (“IC”) containing anti-fuse cells, comprising:
- generating an N-well substrate;
- depositing a drain P+ diffusion layer over a first portion of the N-well substrate;
- depositing a P+ diffusion layer having a drain region and a source region over a second portion of the N-well substrate;
- depositing a source P+ diffusion layer over a third portion of the N-well substrate;
- disposing a first gate oxide over the N-well substrate adjacent to the drain region and the source P+ diffusion layer with portions of the first gate oxide overlaps with the drain region and the source P+ diffusion layer;
- and
- disposing a control gate metal over the first gate oxide.
Dependencies are inferred from the claim text.