Memory device having negative voltage generator
AssigneeSK hynix Inc.
InventorTae Heui KWON
Life of this patent
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Abstract
Provided herein is a voltage generating circuit including: a negative voltage pump configured to generate a first negative voltage; and a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal. The negative voltage regulator includes a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster configured to increase a voltage of the output terminal depending on an output voltage of the first amplifier circuit.
Claims32
A voltage generating circuit comprising:
- a negative voltage pump configured to generate a first negative voltage;
- and
- a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal,
- wherein the negative voltage regulator comprises an amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster configured to increase a voltage of the output terminal depending on an output voltage of the first amplifier circuit.
A memory device comprising:
- a memory cell array;
- a negative voltage pump configured to generate a first negative voltage;
- a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal;
- and
- a row decoder configured to apply the second negative voltage to the memory cell array,
- wherein the negative voltage regulator comprises a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster including a first transistor that is coupled to the output terminal and configured to be controlled an output voltage of the first amplifier circuit, and
- wherein the voltage booster is configured such that the voltage of the output terminal is increased by a charge supplied through the first transistor.
A memory device comprising:
- a memory cell array;
- a negative voltage pump configured to generate a first negative voltage;
- a negative voltage regulator configured to generate a second negative voltage and a third negative voltage higher than the second negative voltage depending on the first negative voltage and output the second negative voltage and the third negative voltage through an output terminal;
- a row decoder configured to successively apply the second negative voltage and the third negative voltage to the memory cell array;
- and
- a page buffer unit configured to store data outputted from the memory cell array in response to the second negative voltage and the third negative voltage,
- wherein the negative voltage regulator comprises a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a first transistor coupled to the output terminal and configured to be controlled by an output voltage of the first amplifier circuit, and
- wherein the voltage of the output terminal is increased from the second negative voltage to the third negative voltage by a charge supplied through the first transistor.
Dependencies are inferred from the claim text.