Memory controller with flexible address decoding

An apparatus having a memory controller, the memory controller comprising:

• a host interface for receiving memory access requests, said memory access requests including access addresses;
• a memory interface for providing memory accesses to a memory system;
• an address decoder coupled to said host interface for programmably mapping said access addresses to selected ones of a plurality of regions, wherein said address decoder is programmable to map said access addresses to a first region having a non-power-of-two size using a primary decoder having a first power-of-two size and a secondary decoder having a second power-of-two size, and provides a first region mapping signal in response;
• a command queue coupled to said address decoder for storing said memory access requests and region mapping signals;
• and
• an arbiter for picking said memory access requests from said command queue based on a plurality of criteria, said plurality of criteria evaluated based in part on said region mapping signals, and providing corresponding memory accesses to said memory interface in response.

An apparatus having a memory controller, the memory controller comprising:

• a host interface for receiving memory access requests, said memory access requests including access addresses;
• a memory interface for providing memory accesses to a memory system, said memory accesses including hashed addresses;
• an address decoder coupled to said host interface for programmably mapping said access addresses to selected ones of a plurality of regions of said memory system using a hashing function, wherein said address decoder is responsive to a plurality of programmable bits to determine which of a corresponding plurality of bits of said access addresses are used in said hashing function;
• a command queue coupled to said address decoder for storing said memory access requests including said hashed addresses;
• and
• an arbiter for picking said memory access requests from said command queue based on a plurality of criteria, and providing corresponding memory accesses including said hashed addresses to said memory interface in response.

A method, comprising:

• receiving memory access requests, said memory access requests including access addresses;
• decoding said access addresses and providing corresponding region mapping signals in response, wherein said decoding includes selectively mapping said access addresses to a first region having a non-power-of-two size using a first primary decoder having a first power-of-two size and a first secondary decoder having a second power-of-two size;
• providing a first region mapping signal in response to mapping said access addresses to said first region;
• storing said memory access requests and region mapping signals;
• and
• picking said memory access requests, so stored, based on a plurality of criteria, said plurality of criteria evaluated based in part on said region mapping signals;
• and
• providing corresponding memory accesses in response to picked memory access requests.

A method comprising:

• receiving memory access requests, said memory access requests including access addresses;
• decoding said access addresses and providing corresponding region mapping signals in response, wherein said decoding includes selectively hashing said access addresses using a hashing function responsive to a plurality of programmable bits to determine which of a corresponding plurality of bits of said access addresses are used in said hashing function;
• providing said region mapping signals in response to said decoding;
• storing said memory access requests and said region mapping signals;
• picking said memory access requests, so stored, based on a plurality of criteria, said plurality of criteria evaluated based in part on said region mapping signals;
• and
• providing corresponding memory accesses in response to picked memory access requests.