Integrated circuit design method and associated non-transitory computer-readable medium

An integrated circuit (IC) design method, comprising:

• determining a sink current distribution information of a layout by using a computer;
• and
• generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information;
• wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets;
• wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated.

A non-transitory computer-readable medium containing therein instructions which, when executed by a computer, cause the computer to perform the actions comprising:

• performing synthesis upon a register transfer level (RTL) integrated circuit (IC) design to generate a gate level netlist;
• performing place and route (P&R) upon the gate level netlist to generate a layout;
• determining a sink current distribution information of the layout;
• and
• generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information;
• wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets;
• wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated.