Shuffler circuit for lane shuffle in simd architecture
AssigneeQUALCOMM Incorporated
InventorsLiang Han, Xiangdong Jin, Lin Chen, Yun Du, Alexei Vladimirovich Bourd
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Abstract
Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.
Claims29
A device for processing data, the device comprising:
- a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure;
- and
- a shuffler circuit configured to:
- receive data from a source subset of the processing lanes;
- reorder the data received from the source subset of the processing lanes responsive to an instruction instructing at least some of the processing lanes to output data to another one of the processing lanes;
- and
- output the reordered data to the processing lanes, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, and wherein the processing lanes other than the destination subset of the processing lanes discard the received reordered data.
A method of processing data, the method comprising:
- receiving, with a shuffler circuit, data from a source subset of processing lanes of a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure;
- reordering, with the shuffler circuit, the data received from the source subset of the processing lanes responsive to an instruction instructing at least some of the processing lanes to output data to another one of the processing lanes;
- and
- outputting, with the shuffler circuit, the reordered data to the processing lanes, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, and wherein the processing lanes other than the destination subset of the processing lanes discard the received reordered data.
A device for processing data, the device comprising:
- means for receiving data from a source subset of processing lanes of a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure;
- means for reordering the data received from the source subset of the processing lanes responsive to an instruction instructing at least some of the processing lanes to output data to another one of the processing lanes;
- and
- means for outputting the reordered data to the processing lanes, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, and wherein the processing lanes other than the destination subset of the processing lanes discard the received reordered data.
A computer-readable storage medium comprising instructions that when executed cause one or more circuits of a device for processing data to:
- receive data from a source subset of processing lanes of a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure;
- reorder the data received from the source subset of the processing lanes responsive to an instruction instructing at least some of the processing lanes to output data to another one of the processing lanes;
- and
- output the reordered data to the processing lanes, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, and wherein the processing lanes other than the destination subset of the processing lanes discard the received reordered data.
Dependencies are inferred from the claim text.