Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word

A data processor, comprising:

• a system bus coupled to at least one memory and having a data width of N, where N is a positive integer;
• and
• a low energy accelerator processor coupled to the system bus and configured to execute parallel instruction words retrieved from the memory responsive to a memory address from a program controller, and further comprising:
• a load store execution unit configured to load data from a memory location and store the load data to registers in the low energy accelerator processor;
• a load coefficient execution unit configured to load data from a one selected from the memory and a ROM and to store the data into a destination register;
• a multiply execution unit configured to perform multiply operations on data from registers and store a result in a destination register;
• and
• a ALU execution unit configured to perform butterfly and ADD operations on data from registers and store a result in a destination register;
• wherein the parallel instruction words have a length of less than or equal to N, the data width of the system bus.