Reducing over-purging of structures associated with address translation
AssigneeInternational Business Machines Corporation
InventorsJonathan D. Bradbury, Christian Jacobi, Anthony Saporito
Life of this patent
Estimating the term…
Abstract
A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes a purging capability that limits the purging of translation look-aside buffers and other such structures based on the marking.
Claims20
A computer program product for managing purging of structure entries associated with address translation, said computer program product comprising:
- a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- determining, by a processor, whether a block of memory for which a purge request has been received is backing an address translation structure, the block of memory having an address to identify the block of memory;
- and
- based on determining the block of memory is not backing the address translation structure, performing an action to selectively purge from a structure associated with address translation entries created from translating the address that are at one level of translation, wherein other entries at one or more other levels of translation created from translating the address remain in the structure.
A computer system for managing purging of structure entries associated with address translation, said computer system comprising:
- a memory;
- and
- a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
- determining, by the processor, whether a block of memory for which a purge request has been received is backing an address translation structure, the block of memory having an address to identify the block of memory;
- and
- based on determining the block of memory is not backing the address translation structure, performing an action to selectively purge from a structure associated with address translation entries created from translating the address that are at one level of translation, wherein other entries at one or more other levels of translation created from translating the address remain in the structure.
A computer-implemented method of managing purging of structure entries associated with address translation, said computer-implemented method comprising:
- determining, by a processor, whether a block of memory for which a purge request has been received is backing an address translation structure, the block of memory having an address to identify the block of memory;
- and
- based on determining the block of memory is not backing the address translation structure, performing an action to selectively purge from a structure associated with address translation entries created from translating the address that are at one level of translation, wherein other entries at one or more other levels of translation created from translating the address remain in the structure.
Dependencies are inferred from the claim text.