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US 2018/0018266 A1Published application
Stride prefetcher for inconsistent strides
AssigneeAdvanced Micro Devices, Inc.
InventorWilliam Evan Jones, III
Life of this patent
Estimating the term…
Abstract
A processing system includes a cache and a prefetcher to prefetch lines from a memory into the cache. The prefetcher receives a memory access request to a first address in the memory and sets a stride length associated with an instruction that issued the memory access request to a length of a line in the cache. The stride length indicates a number of bytes between addresses of lines that are prefetched from the memory into the cache.
Claims20
A method comprising:
- receiving, at a processor, a memory access request to a first memory address issued during execution of an instruction at the processor;
- and
- setting, at the processor, a stride length associated with the instruction to a length of a line in a cache, wherein the stride length indicates a number of bytes between addresses of lines that are prefetched from the memory into the cache.
An apparatus comprising:
- a cache;
- and
- a prefetcher to prefetch lines from a memory into the cache, wherein the prefetcher is to receive a memory access request to a first memory address issued during execution of an instruction and set a stride length associated with an instruction that issued the memory access request to a length of a line in the cache, wherein the stride length indicates a number of bytes between addresses of lines that are prefetched from the memory into the cache.
An apparatus comprising:
- a memory;
- a cache hierarchy connected to the memory;
- and
- a prefetcher to prefetch lines from the memory into at least one cache in the cache hierarchy, wherein the prefetcher is to receive a memory access request to a first memory address issued during execution of an instruction and set a stride length associated with an instruction that issued the memory access request to a length of a line in the at least one cache, wherein the stride length indicates a number of bytes between addresses of lines that are prefetched from the memory into the at least one cache.
1 more element
Dependencies are inferred from the claim text.