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US 2018/0018262 A1Published application
Processor performance monitor that logs reasons for reservation loss
AssigneeInternational Business Machines Corporation
InventorsShakti Kapoor, John A. Schumann, Karen E. Yokum
Life of this patent
Estimating the term…
Abstract
A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.
Claims23
An integrated circuit processor comprising:
- a performance monitor that detects and logs a plurality of reservation losses in the processor and additionally determines and logs a reason for at least one of the plurality of reservation losses.
A method for logging reservation losses in an integrated circuit processor, the method comprising:
- detecting a plurality of reservation losses in the processor;
- determining a reason for at least one of the plurality of reservation losses;
- logging the plurality of reservation losses;
- and
- logging the reason for the at least one of the plurality of reservation losses.
2 more elements
An integrated circuit processor comprising:
- a cache memory that includes a plurality of cache lines, wherein a reservation for a specified memory address comprises a reservation for a cache line that includes the specified memory address;
- a performance monitor that logs a plurality of reservation losses in the processor and additionally logs a reason for at least one of the plurality of reservation losses, wherein a reservation loss occurs between a first instruction that gains a reservation on a specified memory address and a second instruction that completes operations on the specified memory address, wherein the first instruction comprises a Load and Reserve Indexed (larx) instruction and the second instruction comprises a Store Conditional Indexed (stcx) instruction defined in an instruction set for a PowerPC processor, wherein the reservation for the cache line is lost when a store is made to a second memory address in the cache line after the first instruction is executed by the processor and before the second instruction is executed by the processor;
- and
- a load/store unit that indicates to the performance monitor when a reservation loss is due to a store to the cache line that includes the specified memory address.
1 more element
A method for logging reservation losses in an integrated circuit processor, the method comprising:
- detecting a plurality of reservation losses in the processor, wherein a reservation loss occurs between a first instruction that gains a reservation on a specified memory address and a second instruction that completes operations on the specified memory address, wherein the first instruction comprises a Load and Reserve Indexed (larx) instruction and the second instruction comprises a Store Conditional Indexed (stcx) instruction defined in an instruction set for a PowerPC processor, wherein a reservation for the specified memory address comprises a reservation for a cache line that includes the specified memory address, wherein the reservation for the cache line is lost when a store is made to a second memory address in the cache line after the first instruction is executed by the processor and before the second instruction is executed by the processor;
- determining from a load/store unit in the processor a reason for at least one of the plurality of reservation losses;
- logging the plurality of reservation losses;
- sampling addresses that have one of the plurality of reservation losses;
- and
- logging the reason for the reservation loss at each sampled address.
3 more elements
A method for identifying bad programming in a computer program, the method comprising:
- while executing the computer program, an integrated circuit processor performing the steps of:
- detecting a plurality of reservation losses in the processor, wherein a reservation loss occurs between a first instruction that gains a reservation on a specified memory address and a second instruction that completes operations on the specified memory address, wherein the first instruction comprises a Load and Reserve Indexed (larx) instruction and the second instruction comprises a Store Conditional Indexed (stcx) instruction defined in an instruction set for a PowerPC processor, wherein a reservation for the specified memory address comprises a reservation for a cache line that includes the specified memory address, wherein the reservation for the cache line is lost when a store is made to a second memory address in the cache line after the first instruction is executed by the processor and before the second instruction is executed by the processor;
- determining from a load/store unit in the processor a reason for at least one of the plurality of reservation losses;
- logging the plurality of reservation losses;
- sampling addresses that have one of the plurality of reservation losses;
- and
- logging the reason for the reservation loss at each sampled address;
- stopping execution of the computer program;
- querying the logged plurality of reservation losses and the logged reasons for the reservation loss at each sampled address;
- and
- identifying from the logged reasons for the reservation loss at each sampled address the bad programming in the computer program.
8 more elements
Dependencies are inferred from the claim text.