Apparatus and method for low power low latency high capacity storage class memory
AssigneeWestern Digital Tecnologies, Inc.
InventorsFrank R. CHU, Luiz M. FRANCA-NETO, Timothy K. TSAI, Qingbo WANG
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Abstract
A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.
Claims17
An apparatus, comprising:
- a direct attached dual in line memory card with at least one memory unit of dynamic random access memory;
- at least one nonvolatile memory;
- at least one processing unit;
- a memory containing a control code for access by the at least one processing unit;
- and
- at least one memory electrical interface circuit.
A method for operating a memory, comprising:
- buffering a set of data in a dynamic random access memory;
- writing the set of data into a NAND flash memory;
- and
- selectively migrating the set of data from the NAND flash memory to a dynamic random access memory, a phase-change memory, a resistive random access memory, a spin-torque transfer random access memory and the NAND flash memory based on a size of the set of data.
A method for operating a memory, comprising:
- identifying a dynamic access memory size available for use in storage and as a write buffer;
- using a smart decision algorithm on a data set to be stored to determine a data set activity level and a categorization type;
- storing the data set in an arrangement having a dynamic random access memory and at least one of a phase-change memory, a resistive random access memory, a spin-torque transfer random access memory and a NAND flash memory based on at least one of a density, a data set size, the data set activity level and the categorization type.
An apparatus, comprising:
- a direct attached dual in line memory card with at least one memory unit of dynamic random access memory;
- at least one processing unit;
- at least one phase change memory;
- at least one NAND flash memory wherein the NAND flash memory is partitioned into single-level cell and multi-level cell types;
- a plurality of bus buffers;
- and
- at least one memory electrical interface circuit.
A method for operating a memory, comprising:
- obtaining a read operation for a set of data that is contained in at least two different memories wherein a first memory has a first latency and a second memory has a second latency;
- determining which of the first memory and the second memory has a lower latency;
- reading data from the lower latency of the first memory and the second memory;
- and
- reading a remainder of the data from a higher latency of the first memory and the second memory.
A method for operating a memory, comprising:
- obtaining a read operation for a set of data that is contained in at least two different memories wherein a first memory has a first latency and a second memory has a second latency;
- determining which of the data in the first memory and the second memory can be supplied to a user faster based on both latency and bus speed;
- reading data from the first memory and the second memory that has been determined to be faster;
- and
- reading a remainder of the set of data from the first memory and the second memory not previously read.
A method for operating a memory, comprising:
- obtaining a read operation for a set of data that is contained in at least three different memories wherein a first memory has a first latency, a second memory has a second latency and a third memory has a third latency;
- determining which of the data in the first memory, the second memory and the third memory can be supplied to a user faster based on both latency and bus speed;
- reading data from the first memory, the second memory and the third memory that has been determined to be faster;
- reading a remainder of the set of data from the first memory and the second memory not previously read.
A method for operating a memory, comprising:
- obtaining a read operation for a set of data that is contained in at least three different memories wherein a first memory has a first latency, a second memory has a second latency and a third memory has a third latency;
- determining which of the data in the first memory, the second memory and the third memory can be supplied to a user faster based on latency, bus speed and a size of partitions of the set of data;
- reading data from the first memory, the second memory and the third memory that has been determined to be faster;
- reading a remainder of the set of data from the first memory and the second memory not previously read.
Dependencies are inferred from the claim text.