Semiconductor memory device

A semiconductor memory device comprising:

• a first memory array having a plurality of first memory cells arranged in a matrix having a plurality of columns and a plurality of rows;
• a second memory array adjacent to the first memory array and having a plurality of second memory cells, each second memory cell including a transistor having a source electrically connected to one of two predetermined voltages;
• a plurality of word lines extending across the first memory array and the second memory array, each word line electrically connected to one of the first memory cells and electrically connected to one of the second memory cells;
• an address decoder configured to receive input address information and select a word line from the plurality of word lines based on the input address information, wherein a second memory cell of the second memory cells, a gate of a transistor of which is electrically connected to the selected word line, is turned on to enable the second memory cell to output one of the two predetermined voltages electrically connected to a source of the second memory cell to represent address information;
• a latch circuit for latching the input address information;
• and
• a comparison circuit configured to compare the input address information latched by the latch circuit with the address information read from the second memory array.