US 2018/0018190 A1 · DELAYING PURGING OF STRUCTURES ASSOCIATED WITH ADDRESS TRANSLATION

Abstract

Virtual machine purging of structures associated with address translation is delayed. A host logical processor executing on a physical processor issues a local purge request to purge entries of a structure associated with address translation. The structure associated with address translation includes one or more host entries for the host logical processor and one or more guest entries for a guest virtual processor running on the physical processor. Based on issuing the local purge request, an indicator is set to control purging of the one or more guest entries of the structure associated with address translation. Further, purging of the one or more guest entries of the guest virtual processor is delayed for consideration of purging at dispatch of the guest virtual processor.

Claims20

Dependent claims

A computer program product for facilitating processing in a computing environment, said computer program product comprising:

a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
issuing, by a host logical processor executing on a physical processor, a local purge request to purge entries of a structure associated with address translation, the structure associated with address translation including one or more host entries for the host logical processor and one or more guest entries for a guest virtual processor running on the physical processor;
and
based on issuing the local purge request, setting an indicator to control purging of the one or more guest entries of the structure associated with address translation, and delaying purging of the one or more guest entries of the guest virtual processor for consideration of purging at dispatch of the guest virtual processor.

1 more element

A computer system for facilitating processing in a computing environment, said computer system comprising:

a memory;
and
a physical processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
issuing, by a host logical processor executing on the physical processor, a local purge request to purge entries of a structure associated with address translation, the structure associated with address translation including one or more host entries for the host logical processor and one or more guest entries for a guest virtual processor running on the physical processor;
and
based on issuing the local purge request, setting an indicator to control purging of the one or more guest entries of the structure associated with address translation, and delaying purging of the one or more guest entries of the guest virtual processor for consideration of purging at dispatch of the guest virtual processor.

3 more elements

A computer-implemented method of facilitating processing in a computing environment, said computer-implemented method comprising:

issuing, by a host logical processor executing on a physical processor, a local purge request to purge entries of a structure associated with address translation, the structure associated with address translation including one or more host entries for the host logical processor and one or more guest entries for a guest virtual processor running on the physical processor;
and
based on issuing the local purge request, setting an indicator to control purging of the one or more guest entries of the structure associated with address translation, and delaying purging of the one or more guest entries of the guest virtual processor for consideration of purging at dispatch of the guest virtual processor.

Dependencies are inferred from the claim text.

Delaying purging of structures associated with address translation

Life of this patent

Delaying purging of structures associated with address translation

Life of this patent

Abstract

Claims20