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US 2018/0018170 A1Published application
Compressed Instruction Format
AssigneeIntel Corporation
InventorsRobert Valentine, Doron Orenstein, Bret L. Toll
Life of this patent
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Abstract
A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
Claims1
An apparatus comprising:
- a first instruction decode logic to indicate to a second instruction decode logic the function of each of a plurality of fields within an instruction, wherein the second instruction decode logic is to use the function of each of the plurality of fields indicated by the first instruction decode logic to translate the instruction from a first format to a second format, wherein the second format is to represent at least one of the plurality of fields with fewer bits than the first format of the instruction.
Dependencies are inferred from the claim text.