Memory controller arbiter with streak and read/write transaction management

An apparatus comprising a memory controller, said memory controller comprising:

• a decoder for receiving memory access requests and decoding each memory access request into a type;
• a command queue coupled to said decoder for receiving and storing decoded memory access requests;
• and
• an arbiter for picking said memory access requests from said command queue based on a plurality of criteria and for providing picked memory access requests to a memory channel, wherein:
• said type indicates whether a corresponding memory access request is a read request or a write request;
• said arbiter scans said command queue and counts a number of memory access requests of a first type, wherein said first type is a selected one of said read request and said write request;
• and
• when said number of memory access requests of said first type is greater than or equal to a first threshold, said arbiter suspends picking memory access requests of a second type and provides at least one memory access request of said first type to said memory channel, wherein said second type is a different one of said read request and said write request than said first type.

A method for sequencing memory access requests to a dynamic random access memory system, said method comprising:

• receiving memory access requests;
• storing said memory access requests in a command queue, wherein said memory access requests comprise memory access requests of a first type, and at least one memory access request of a second type;
• executing a streak of consecutive memory access requests of said first type until a first threshold is reached, wherein said command queue stores at least one additional memory access request of said first type and said at least one memory access request of said second type;
• and
• executing said at least one memory access request of said second type after executing said memory access requests of said first type.

A method for sequencing memory access requests to a dynamic random access memory system, said method comprising:

• receiving memory access requests;
• decoding said memory access requests into a type, wherein said type indicates whether a corresponding memory access request is a read request or a write request;
• storing decoded memory access requests including said type in a command queue;
• and
• picking said memory access requests from said command queue based on a plurality of criteria, wherein said picking comprises:
• scanning said command queue and counting a number of memory access requests of a first type, wherein said first type is a selected one of said read request and said write request;
• and
• when said number of memory access requests of said first type is greater than or equal to a first threshold, suspending picking said memory access requests of a second type and providing at least one memory access request of said first type to a memory channel, wherein said second type is a different one of said read request and said write request than said first type.