Memory device including data processor and program method of same
AssigneeWinbond Electronics Corp.
InventorJohnny CHAN
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory array including a plurality of memory cells that store data, a sense circuit coupled to the memory array for reading data stored in the memory array, a data register for storing data to be written into the memory array, a data processor, and a control unit. The data processor is configured to receive input data units to be written into the memory array, and process the input data units based on array data units stored in the memory array to generate processed data units. The control unit is configured to write the processed data units into the memory array.
Claims19
A memory device, comprising:
- a memory array including a plurality of memory cells that store data;
- a sense circuit coupled to the memory array for reading data stored in the memory array;
- a data register for storing data to be written into the memory array;
- a data processor configured to:
- receive input data units to be written into the memory array;
- process the input data units based on array data units stored in the memory array to generate processed data units;
- and
- write the processed data units into the data register;
- and
- a control unit configured to write the processed data units in the data register into the memory array.
A method for programming a memory array, comprising:
- receiving input data units to be written into the memory array;
- processing the input data units based on array data units stored in the memory array to generate processed data units;
- writing the processed data units into a data register;
- and
- writing the processed data units in the data register into the memory array.
A method for programming a memory array, comprising:
- receiving an initial address;
- receiving a first input data unit to be written into the memory array at the initial address;
- reading a first array data unit from the memory array at the initial address;
- processing the first input data unit based on the first array data unit to generate a first processed data unit;
- writing the first processed data unit into a data register and associating the first processed data unit with the initial address;
- incrementing the initial address to generate an incremented address;
- receiving a second input data unit to be written into the memory array at the incremented address;
- reading a second array data unit from the memory array at the incremented address;
- processing the second input data unit based on the second array data unit to generate a second processed data unit;
- writing the second processed data unit into the data register and associating the second processed data unit with the incremented address;
- and
- writing the first and second processed data units in the data register into the memory array,
- wherein processing the first input data unit based on the first array data unit to generate a first processed data unit and writing the first processed data unit into the data register are performed while receiving the second input data unit.
Dependencies are inferred from the claim text.