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US 2018/0018128 A1Published application
Memory system
AssigneeSK hynix Inc.
InventorTai Kyu KANG
Life of this patent
Estimating the term…
Abstract
Provided herein is a memory device including a memory cell array, a peripheral circuit configured to perform a first operation for the memory cell array, and a control circuit configured to generate an operation status code and output the operation status code. The first operation includes a plurality of second operations that are successively performed. The operation status code indicates, among the plurality of second operations, a current operation that is being performed by the peripheral circuit.
Claims20
A memory device comprising:
- a memory cell array;
- a peripheral circuit configured to perform an operation for the memory cell array the operation including a plurality of sub-operations;
- and
- a control circuit configured to generate an operation status code for the memory device and output the operation status,
- wherein the operation status code indicates, a current sub-operation that is being performed by the peripheral circuit.
2 more elements
A memory device comprising:
- a memory cell array;
- a peripheral circuit configured to perform an operation for the memory cell array in response to a command;
- and
- a control circuit configured to generate an operation status code and output the operation status code in response to an operation status read command,
- wherein the operation comprises a plurality of sub-operations that are successively performed, and
- wherein, every time each of the plurality of sub-operations is performed, the operation status code is changed to a value corresponding to a current sub-operation that is being performed.
3 more elements
A memory system comprising:
- a memory controller configured to output a first command and an operation status read command;
- and
- a first memory device configured to perform a first operation including a plurality of sub-operations that are successively performed in response to the first command, generate an operation status code indicating that any one of the plurality of sub-operations is being performed, and output the operation status code to the memory controller in response to the operation status read command.
Dependencies are inferred from the claim text.