Two stage command buffers to overlap iommu map and second tier memory reads
AssigneeGoogle Inc.
InventorsMonish Shah, Benjamin Charles Serebrin, Albert Borchers
Life of this patent
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Abstract
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.
Claims19
A method, comprising:
- copying, in a first stage using one or more processors, data from a given second tier memory address into an internal buffer of a storage controller, the copying at least partially occurring during mapping by an operating system of a specified physical address into an input/output memory management unit (IOMMU);
- determining, with the one or more processors, whether a second stage is triggered;
- and
- if the second stage is triggered, copying, with the one or more processors, the data from the internal buffer of the storage controller to the specified physical address of dynamic random access memory (DRAM).
A method, comprising:
- identifying a particular second tier memory address storing data;
- allocating a page at a particular physical address of dynamic random access memory (DRAM);
- sending a command to a storage controller, the command identifying the particular second tier memory address and the particular physical address and initiating a first stage in which the stored data is read from the particular second tier memory address into a buffer of the storage controller;
- mapping the particular physical address into an input/output memory management unit (IOMMU), the mapping at least partially occurring during the first stage reading;
- and
- editing the command to the storage controller to initiate a second stage in which the stored data is written from the storage controller buffer to the particular DRAM physical address.
A storage controller, comprising:
- a memory including a buffer;
- one or more processors in communication with the memory, the one or more processors to:
- copy, in a first stage, data from a given second tier memory address into the buffer of the storage controller, the copying at least partially occurring during mapping by an operating system of a specified physical address into an input/output memory management unit (IOMMU);
- determine whether a second stage is triggered;
- and
- if the second stage is triggered, copy the data from the buffer of the storage controller to the specified physical address of dynamic random access memory (DRAM).
Dependencies are inferred from the claim text.