Dynamic write latency for memory controller using data pattern extraction
AssigneeAdvanced Micro Devices, Inc.
InventorsAmin Farmahini Farahani, Benjamin Y. Cho, Nuwan Jayasena
Life of this patent
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Abstract
Methods and apparatus of dynamically determining a variable reset latency time based on a data pattern of the data to be written into memory is disclosed. A memory controller determines a variable reset latency time for a plurality of memory cells depending on the bit values to be written into the plurality of memory cells in response to a write request having corresponding bit values. A write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells. The memory controller writes the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.
Claims20
A method, carried out by a memory controller, the method comprising:
- determining a variable reset latency time for a plurality of memory cells depending on bit values to be written into a plurality of memory cells, in response to a write request having the corresponding bit values, wherein a write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells;
- and
- writing the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.
A memory controller comprising:
- a variable reset latency determination logic configured to:
- determine a variable reset latency time for a plurality of memory cells depending on the bit values to be written into a plurality of memory cells in response to a write request having corresponding bit values, wherein a write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells;
- and
- write the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.
An apparatus comprising:
- a plurality of memory cells;
- a write request source configured to send a write request;
- a memory controller communicatively coupled to the plurality of memory cells and the write request source, the memory controller comprising:
- a variable reset latency determination logic configured to:
- determine a variable reset latency time for the plurality of memory cells depending on bit values to be written into the plurality of memory cells, in response to receiving the write request having the corresponding bit values, wherein a write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells;
- and
- write the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.
Dependencies are inferred from the claim text.