# US 2018/0018095 A1 · Method of operating storage device and method of operating data processing system including the device

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- Number: US 2018/0018095 A1
- Document ID: US20180018095A1
- Status: Published application
- Kind: A1
- Application number: 15/641,576
- Filed: 2017-07-05
- Published: 2018-01-18
- Earliest claimed: 2016-07-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jeong Ho LEE; Jin Woo KIM; Young Jin CHO
- Web page: https://patentgrep.com/patent/US20180018095A1

## CPC

- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0611: {in relation to response time}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence)
- G06F 2212/65: Details of virtual memory and virtual address translation
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of operating a data storage device which includes a first memory device, a second memory device, and a memory device storing a translation map is provided. The method includes receiving either a first identifier (ID) or a second ID and a virtual address from a host, selecting one of a first physical address and a second physical address from the translation map using either the first ID or the second ID and the virtual address, and reading data from one of the first memory device and the second memory device using the selected physical address and transmitting the data to the host. The translation map includes information about mapping the first ID and the virtual address to the first physical address of the first memory device and information about mapping the second ID and the virtual address to the second physical address of the second memory device.

## Claims

### Claim 1

A method of operating a data storage device, the data storage device including a first memory device, a second memory device, and a third memory device storing a translation map, the method comprising:
receiving, an identifier and a virtual address from a host, the identifier being one of a first ID and a second ID;
selecting one of a first physical address and a second physical address using the translation map based on the received identifier and the virtual address,
the translation map including first information related to a mapping of the first ID and the virtual address to the first physical address of the first memory device, and second information about a mapping of the second ID and the virtual address to the second physical address of the second memory device; and
reading data from one of the first memory device and the second memory device based on the selected physical address; and
transmitting the read data to the host.

### Claim 2 (depends on 1)

The method of claim 1, wherein
the first ID is a first process ID of a first process executed in a processor of the host; and
the second ID is a second process ID of a second process executed in the processor.

### Claim 3 (depends on 1)

The method of claim 1, wherein
when the host includes at least one multi-core processor including a first core and a second core,
the first ID includes a first core ID of the first core and a process ID, and
the second ID includes a second core ID of the second core and the process ID; and
the process ID indicates a process executed in either of the first core and the second core.

### Claim 4 (depends on 1)

The method of claim 1, wherein the data storage device is a dual in-line memory module.

### Claim 5

A method of operating a data storage device including a first memory device and a second memory device, the method comprising:
receiving a first identifier (ID) and a virtual address from a host;
translating the first ID and the virtual address into a first physical address; and
accessing at least one of the first memory device and the second memory device based on the first physical address.

### Claim 6 (depends on 5)

The method of claim 5, wherein the translating the first ID and the virtual address into the first physical address comprises:
translating the first ID and the virtual address into the first physical address based on a bit value of a flag which identifies at least one of the first memory device or the second memory device.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
reading first data from the accessed memory device corresponding to the first physical address; and
transmitting the first data to the host.

### Claim 8 (depends on 5)

The method of claim 5, further comprising:
receiving a second ID and the virtual address from the host;
translating the second ID and the virtual address into a second physical address; and
accessing at least one of the first memory device and the second memory device based on the second physical address.

### Claim 9 (depends on 8)

The method of claim 8, wherein the translating the second ID and the virtual address into the second physical address comprises:
translating the second ID and the virtual address into the second physical address based on a bit value of a flag which identifies at least one of the first memory device or the second memory device.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
reading second data from the second accessed memory device based on the second physical address; and
transmitting the second data to the host.

### Claim 11 (depends on 5)

The method of claim 5, wherein
the first memory device has a first read latency; and
the second memory device has a second read latency, the second read latency being different from the first read latency.

### Claim 12 (depends on 5)

The method of claim 5, further comprising:
calculating an access delay with respect to a region corresponding to the first physical address; and
transmitting the access delay to the host.

### Claim 13 (depends on 8)

The method of claim 8, wherein
the first ID is an ID of a first process executed in at least one processor of the host; and
the second ID is an ID of a second process executed in the processor.

### Claim 14 (depends on 8)

The method of claim 8, wherein
when the host comprises a multi-core processor including at least a first core and a second core, the first ID is a ID of the first core and the second ID is a ID of the second core.

### Claim 15 (depends on 8)

The method of claim 8, wherein when the host comprises a multi-core processor including at least a first core and a second core:
the first ID includes a ID of the first core and a process ID; and
the second ID includes a second core ID of the second core and the process ID; and
the process ID indicates a process executed in either of the first core and the second core.

### Claim 16 (depends on 8)

The method of claim 8, wherein the first ID and the second ID are received through a dedicated pin formed in the data storage device.

### Claim at position 17

17-20. (canceled)

### Claim 21

A method for operating a data storage device, the data storage device including a plurality of heterogeneous memory devices and a memory controller, the method comprising:
receiving, using the memory controller, a memory operation instruction from a host, the memory operation including at least a process ID and a virtual address;
translating, using the memory controller, the virtual address into a physical address associated with a memory device of the plurality of heterogeneous memory devices using a virtual address-to-physical address translation map stored on a buffer and the process ID; and
performing, using the memory controller, a memory operation at the physical address on the associated memory device in accordance with the memory operation instruction.

### Claim 22 (depends on 21)

The method of claim 21, wherein
the virtual address is a virtual page number; and
the physical address is a physical page number.

### Claim 23 (depends on 21)

The method of claim 21, wherein the translating further includes:
determining, using the memory controller, a value of a flag of the virtual address-to-physical address translation map, the flag value indicating the memory device of the plurality of heterogeneous memory devices.

### Claim 24 (depends on 21)

The method of claim 21, wherein each of the plurality of heterogeneous memory devices has different performance characteristics than the other memory devices of the plurality of heterogeneous memory devices.