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US 2018/0018092 A1Published application
Interface Circuits Configured to Interface with Multi-Rank Memory
AssigneeSamsung Electronics Co., Ltd.
InventorsKwanyeob Chae, Yoonjee Nam, Ji Hun Oh, Shinyoung Yi, Jong-Ryun Choi
Life of this patent
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Abstract
An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
Claims23
An interface circuit comprising:
- a first FIFO circuit configured to generate pieces of first parallel data from a first sampling signal in response to a first edge of a first reference signal, generate pieces of second parallel data from a second sampling signal in response to a second edge of the first reference signal, and generate first output data from the pieces of first parallel data and the pieces of second parallel data in response to a first select signal which is generated based on a first division signal generated by dividing the first reference signal;
- and
- a second FIFO circuit configured to generate pieces of third parallel data from a third sampling signal in response to a first edge of a second reference signal, generate pieces of fourth parallel data from a fourth sampling signal in response to a second edge of the second reference signal, and generate second output data from the pieces of third parallel data and the pieces of fourth parallel data in response to a second select signal that is generated based on a second division signal generated by dividing the second reference signal,
- wherein the second FIFO circuit is configured to be reset by the first division signal before the first output data is output from the first FIFO circuit, and the first FIFO circuit is configured to be reset by the second division signal before the second output data is output from the second FIFO circuit.
1 more element
(canceled)
(canceled)
An interface circuit comprising:
- a sampling circuit configured to generate a first sampling result and a second sampling result by sampling a logic state of a data signal in response to a first edge and a second edge of a data strobe signal, respectively;
- a delay circuit configured to delay the data strobe signal to produce a delayed data strobe signal;
- and
- a FIFO circuit configured to generate pieces of first parallel data from the first sampling result in response to a first edge of the delayed data strobe signal and generate pieces of second parallel data from the second sampling result in response to a second edge of the delayed data strobe signal,
- wherein the FIFO circuit is further configured to generate output data from the pieces of first parallel data and the pieces of second parallel data in response to a select signal generated according to the delayed data strobe signal, and wherein a frequency of the select signal is lower than a frequency of the delayed data strobe signal.
2 more elements
-22. (canceled)
An interface circuit comprising:
- a first sampling circuit configured to generate first sampled data based on a first data signal in response to a first data strobe signal;
- a first divider circuit configured to divide the first data strobe signal to generate a first division signal, a frequency of the first division signal being lower than a frequency of the first data strobe signal;
- a first front end FIFO circuit configured to store the first sampled data based on the first data strobe signal and further configured to generate first output data from the first sampled data in response to a first select signal, the first select signal being generated based on the first division signal, a frequency of the first select signal being lower than a frequency of the first data strobe signal;
- and
- a back end FIFO circuit configured to store the first output data based on the first division signal.
2 more elements
Dependencies are inferred from the claim text.