Baseband processor and method for power saving by adjustment of clock rate and supply voltage

A baseband processor comprising:

• a baseband front end component configured to receive a downlink (DL) baseband (BB) signal in a transmission time interval (TTI), wherein the DL BB signal comprises a time-frequency resource comprising a control section and a data section;
• a demodulation chain configured to decode at least part of the control section;
• and
• a controller configured to detect a DL grant information from the decoded control section and if the DL grant information is detected:
• to determine a number of granted data resource blocks from the DL grant information and to adjust at least one of a clock rate and supply voltage of the baseband processor based on the number of granted resource blocks.

A user equipment (UE), comprising:

• a radio frequency processor configured to transceive radio signals;
• a baseband processor comprising:
• a baseband front end component configured to receive a downlink (DL) baseband (BB) signal in a transmission time interval (TTI), wherein the DL BB signal comprises a time-frequency resource comprising a control section and a data section;
• a demodulation chain configured to decode at least part of the control section;
• and
• a controller configured to detect a DL grant information from the decoded control section and if the DL grant information is detected:
• to determine a number of granted data resource blocks from the DL grant information and to adjust at least one of a clock rate and supply voltage of the baseband processor based on the number of granted resource blocks,
• wherein the baseband processor is configured to process the radio signals transceived by the radio frequency processor in a baseband depending on the clock rate;
• and
• a battery configured to supply at least the baseband processor with the supply voltage.

A processor, comprising:

• a receiver configured to receive a first component carrier signal and a second component carrier signal, wherein each component carrier signal comprises a time-frequency resource comprising a control section and a data section;
• a first decoder configured to decode at least part of the control section of the first component carrier signal;
• a second decoder configured to decode at least part of the control section of the second component carrier signal;
• a controller configured to detect a first DL grant information from the decoded control section of the first component carrier signal and a second DL grant information from the decoded control section of the second component carrier signal, and if the first and second DL grant information are detected:
• to determine a first number of granted data resource blocks from the first DL grant information and a second number of granted data resource blocks from the second DL grant information and to adjust at least one of a clock rate and supply voltage of the processor based on the greater number of the first number and the second number of granted resource blocks.