Hardware acceleration architecture for signature matching applications for deep packet inspection

A method for fetching a next state transition from a compressed deterministic finite automata (DFA) using a processing circuit in a hardware accelerator circuit of signature matching hardware accelerator system, wherein the DFA comprises a state table representing a database of digital signatures defined by a plurality of states and a plurality of characters, wherein the plurality of states are divided into groups, each group comprising a leader state having a plurality of leader state transitions and one or more member states, each having a plurality of member state transitions and wherein each of the member state is associated a member transition bitmask comprising a plurality of bitmasks that identify the member state transitions within the respective member state that are different from the leader state transitions for the respective character, comprising:

• receiving information on a current state and a current input character that defines an incoming data;
• fetching the next state transition for the current state from a leader transition table comprising the plurality of leader state transitions within a memory circuit of the hardware accelerator circuit, when the current state is a leader state;
• and
• fetching the next state transition for the current state selectively from the leader transition table or a member transition table within the memory circuit based on an information of the respective member transition bitmask, when the current state is a member state, wherein the member transition table comprises only the member state transitions of the plurality of member state transitions that are different from the leader state transitions for a respective character within each group.