US 2018/0006851 A1 · THREE PHASE AND POLARITY ENCODED SERIAL INTERFACE

Abstract

A high-speed serial interface is provided. In one aspect, the high-speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high-speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Claims30

Dependent claims

An apparatus, comprising:

a serial interface adapted to communicate encoded data over three conductors;
a first device coupled to the serial interface and configured to:
map a first number of bits of data to a sequence of transitions, wherein the sequence of transitions defines a second number of state transitions on the three conductors;
and
transmit a three-phase signal on each of the three conductors,
wherein the three-phase signal is responsive to the sequence of transitions, and
wherein the signal transmitted on each conductor is 120 degrees out of phase relative to the signals transmitted on the remaining two conductors;
and
a second device coupled to the serial interface and configured to:
receive a signal from each of the three conductors;
determine a sequence of transitions in signaling state of the three conductors;
and
demap the first number of bits of data from the sequence of transitions,
wherein the first number and the second number have different integer values.

11 more elements

A non-transitory processor-readable medium storing computer-executable code, comprising code for causing one or more processors to:

map a first number of bits of data to a sequence of transitions at a first device coupled to a serial interface, wherein the sequence of transitions defines a second number of state transitions on three conductors of the serial interface;
and
transmit a three-phase signal on each of the three conductors from the first device to a second device coupled to the serial interface, wherein the three-phase signal is responsive to the sequence of transitions, and wherein the signal transmitted on each conductor is 120 degrees out of phase relative to the signals transmitted on the remaining two conductors;
receive a signal from each of the three conductors at the second device;
determine, at the second device, the sequence of transitions in signaling state of the three conductors;
and
demap the first number of bits of data from the sequence of transitions,
wherein the first number and the second number have different integer values.

5 more elements

Dependencies are inferred from the claim text.

Three phase and polarity encoded serial interface

Life of this patent

Three phase and polarity encoded serial interface

Life of this patent

Abstract

Claims30