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US 2018/0006848 A1Published application
Low power equalizer and its training
AssigneeIntel Corporation
InventorsLuke A. JOHNSON, Sleiman BOU-SLEIMAN
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Abstract
Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.
Claims20
An apparatus comprises:
- a pad to receive an input signal;
- an electro-static discharge (ESD) unit coupled to a pad;
- and
- a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.
1 more element
An apparatus comprising:
- samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE);
- and
- logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same.
A system comprising:
- memory unit;
- a processor coupled to the memory unit, the processor including an apparatus which comprises:
- a pad to receive an input signal:
- an electro-static discharge (ESD) unit coupled to a pad:
- and
- a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal;
- a wireless interface for allowing the processor to communicate with another device.
4 more elements
Dependencies are inferred from the claim text.