Dual-mode processing of cryptographic operations

A computer system comprising:

• a cryptographic hardware accelerator;
• a host central processing unit (CPU), coupled to the cryptographic hardware accelerator, having a plurality of native hardware supported cryptographic operations;
• wherein responsive to receiving by the host CPU data upon which a cryptographic operation is to be performed, the CPU performs a method comprising:
• dividing the data into a plurality of blocks;
• offloading performance of the cryptographic operation on a first block of the plurality of blocks to the cryptographic hardware accelerator;
• for each remaining block of the plurality of blocks:
• requesting state information associated with the cryptographic hardware accelerator;
• when the state information satisfies a predetermined condition, then offloading performance of the cryptographic operation on the remaining block to the cryptographic hardware accelerator;
• when the state information does not satisfy the predetermined condition, then performing the cryptographic operation on the remaining block by invoking a native hardware supported cryptographic instruction of the plurality of native hardware supported cryptographic operations on the remaining block;
• and
• wherein the cryptographic operation is performed on at least one of the plurality of blocks by the cryptographic hardware accelerator and the cryptographic operation is performed on at least another of the plurality of blocks by the CPU.