Clock-and-data recovery (cdr) circuitry for performing automatic rate negotiation
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsAjay Yadav, Samir Aboulhouda, Faouzi Chaahoub
Life of this patent
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Abstract
A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.
Claims20
Clock and data recovery (CDR) circuitry configured to determine whether an incoming data signal has one of at least a first, second and third data rate and to perform CDR on the incoming data signal when the incoming data signal has one of the second and third data rates and to bypass performing CDR when the incoming data signal has the first data rate.
Clock and data recovery (CDR) circuitry comprising:
- an equalizer having an input and an output, input receiving an incoming data signal having one of a first, second and third data rate, the equalizer outputting an equalized data signal from the output thereof;
- a phase-locked loop (PLL) configured to attempt to frequency and phase lock a frequency and phase of a reference clock to a frequency and phase of the equalized data signal, respectively, and to output a recovered, retimed data signal from an output of a phase detector of the PLL, an input of the phase detector being electrically coupled to the output of the equalizer;
- a first switching circuit having first and second inputs and an output, the first and second inputs of the first switching circuit being electrically coupled to the outputs of the equalizer and the phase detector, respectively;
- and
- data rate determination and control logic configured to determine which of the first, second and third data rates the incoming electrical data signal has and to place the first switching circuit in one of a CDR bypass mode of operations and a CDR mode of operations based on the determined data rate of the incoming data signal, wherein in the CDR mode of operations, the recovered, retimed data signal is output from the first switching circuit, and wherein in the CDR bypass mode of operations, the equalized data signal is output from the first switching circuit.
A method for performing data rate negotiation in clock and data recovery (CDR) circuitry, the method comprising:
- receiving an incoming data signal having one of a first, second and third data rate;
- determining which of the first, second and third data rates the incoming data signal has;
- placing the CDR circuitry in one of a CDR bypass mode of operations and a CDR mode of operations based on the determined data rate of the incoming data signal;
- outputting the incoming data signal from an output of the CDR circuitry without performing CDR when the CDR circuit is in the bypass mode of operations;
- and
- performing CDR on the incoming data signal and outputting a recovered, retimed data signal from the output of the CDR circuitry when the CDR circuitry is in the CDR mode of operations.
Dependencies are inferred from the claim text.