US 2018/0006794 A1 · FULL-DUPLEX SELF-INTERFERENCE CANCELLATION

Abstract

This disclosure describes methods and devices related to self-interference cancellation. A device is disclosed comprising: at least one memory storing computer-executable instructions; and at least one processor configured to access the at least one memory, wherein the at least one processor may be configured to execute the computer-executable instructions to cause to send at least one first symbol sequence at least twice on a first transmit chain and at least one second symbol sequence twice on a second transmit chain. The processor may be configured to execute the computer-executable instructions to determine at least one third symbol sequence at least twice on a first receive chain and at least one fourth symbol sequence at least twice on a second receive chain. The processor may be configured to execute the computer-executable instructions to determine a first impulse response of a first power amplifier on the first transmit chain and a second impulse response of a second power amplifier on the second transmit chain. The processor may be configured to execute the computer-executable instructions to determine a first aggregate impulse response associated with one or more first devices on the first transmit chain and the first receive chain. The processor may be configured to execute the computer-executable instructions to determine a second aggregate impulse response associated with one or more second devices on the second transmit chain and the second receive chain. The processor may be configured to execute the computer-executable instructions to determine a third impulse response based at least in part on the first and second impulse response, and the first and second aggregate impulse response. The processor may be configured to execute the computer-executable instructions to determine an estimate of the third impulse response based at least in part on the at least one first symbol sequence or the at least one second symbol sequence.

Claims28

Dependent claims

A device comprising:

at least one memory storing computer-executable instructions;
and
at least one processor configured to access the at least one memory, wherein the at least one processor is configured to execute the computer-executable instructions to:
cause to send at least one first symbol sequence at least twice on a first transmit chain and at least one second symbol sequence twice on a second transmit chain;
determine at least one third symbol sequence at least twice on a first receive chain and at least one fourth symbol sequence at least twice on a second receive chain;
determine a first impulse response of a first power amplifier on the first transmit chain and a second impulse response of a second power amplifier on the second transmit chain;
determine a first aggregate impulse response associated with one or more first devices on the first transmit chain and the first receive chain;
determine a second aggregate impulse response associated with one or more second devices on the second transmit chain and the second receive chain;
determine a third impulse response based at least in part on the first and second impulse response, and the first and second aggregate impulse response;
and
determine an estimate of the third impulse response based at least in part on the at least one first symbol sequence or the at least one second symbol sequence.

8 more elements

A non-transitory computer-readable medium including instructions stored thereon, which when executed by one or more processors of a device, cause the one or more processors to perform operations comprising:

causing to send at least one first symbol sequence at least twice on a first transmit chain and at least one second symbol sequence twice on a second transmit chain;
determining at least one third symbol sequence at least twice on a first receive chain and at least one fourth symbol sequence at least twice on a second receive chain;
determining a first impulse response of a first power amplifier on the first transmit chain and a second impulse response of a second power amplifier on the second transmit chain;
determining a first aggregate impulse response associated with one or more first devices on the first transmit chain and the first receive chain;
determining a second aggregate impulse response associated with one or more second devices on the second transmit chain and the second receive chain;
determining a third impulse response based at least in part on the first and second impulse response, and the first and second aggregate impulse response;
and
determining an estimate of the third impulse response based at least in part on the at least one first symbol sequence or the at least one second symbol sequence.

5 more elements

A device comprising:

a first power amplifier and a second power amplifier;
a first circulator and a second circulator;
a first low noise amplifier and a second low noise amplifier;
a first analog self-interference cancellation filter and a second analog self-interference cancellation filter;
and
a modem, wherein the modem:
transmits at least one first symbol sequence at least twice on a first transmit chain comprising the first power amplifier and the first circulator;
transmits at least one second symbol sequence at least twice on the second transmit chain comprising the second power amplifier and the second circulator;
determines at least one third symbol sequence at least twice on a first receive chain comprising the first low noise amplifier, the first circulator, and the first analog self-interference cancellation filter;
determines at least one fourth symbol sequence at least twice on a second receive chain comprising the second low noise amplifier, the second circulator, and the second analog self-interference cancellation filter;
determines a first impulse response of the first power amplifier;
determines a second impulse response of the second power amplifier;
determines a first aggregate impulse response of the first receive chain;
determines a second aggregate impulse response of the second receive chain;
determines a third impulse response based at least in part on the first impulse response of the first power amplifier and second impulse response of the second power amplifier, and the first and second aggregate impulse responses;
and
determines an estimate of the third impulse response based at least in part on the at least one first symbol sequence or the at least one second symbol sequence.

14 more elements

Dependencies are inferred from the claim text.

Full-duplex self-interference cancellation

Life of this patent

Full-duplex self-interference cancellation

Life of this patent

Abstract

Claims28