Decoding method, memory controlling circuit unit and memory storage device
AssigneePhison Electronics Corp.
InventorChih-Kang Yeh
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Abstract
A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.
Claims24
A decoding method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of memory cells, the decoding method comprising:
- performing a first type decoding operation for a first frame comprising a first codeword to obtain a second codeword;
- recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation;
- updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition;
- and
- performing a second type decoding operation for a block code comprising the first frame.
A memory controlling circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, wherein the memory controlling circuit unit comprises:
- a host interface, configured to couple to a host system;
- a memory interface, configured to couple to the rewritable non-volatile memory module;
- a memory management circuit, coupled to the host interface and the memory interface;
- and
- an error checking and correcting circuit, coupled to the memory management circuit, and configured to perform a first type decoding operation for a first frame comprising a first codeword to obtain a second codeword,
- wherein the memory management circuit is configured to record error estimate information corresponding to the first frame according to an execution result of the first type decoding operation,
- wherein the memory management circuit is further configured to update the first codeword in the first frame to the second codeword if the error estimate information matches a first condition,
- wherein the error checking and correcting circuit is further configured to perform a second type decoding operation for a block code comprising the first frame.
A memory storage device, comprising:
- a connection interface unit, configured to couple to a host system;
- a rewritable non-volatile memory module comprising a plurality of memory cells;
- and
- a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
- wherein the memory controlling circuit unit is configured to perform a first type decoding operation for a first frame comprising a first codeword to obtain a second codeword,
- wherein the memory controlling circuit unit is configured to record error estimate information corresponding to the first frame according to an execution result of the first type decoding operation,
- wherein the memory controlling circuit unit is further configured to update the first codeword in the first frame to the second codeword if the error estimate information matches a first condition,
- wherein the memory controlling circuit unit is further configured to perform a second type decoding operation for a block code comprising the first frame.
Dependencies are inferred from the claim text.