Methods and apparatus for performing reed-solomon encoding by lagrangian polynomial fitting
AssigneeAltera Corporation
InventorsMartin Langhammer, Simon Finn, Sami Mumtaz
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Abstract
An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may receive a message and generate corresponding partial syndromes. The matrix multiplication circuitry may receive the partial syndromes and may compute parity check symbols by multiplying the partial syndromes by predetermined Lagrangian polynomial coefficients. The parity check symbol generation step may be performed in one clock cycle or multiple clock cycles.
Claims20
An integrated circuit, comprising:
- partial syndrome calculation circuitry that receives a message and that generates corresponding partial syndrome values;
- and
- matrix multiplication circuitry that receives the partial syndrome values from the partial syndrome calculation circuitry and that generates corresponding parity symbols.
A method for operating an integrated circuit, comprising:
- with partial syndrome calculation circuitry in the integrated circuit, receiving a message and generating partial syndromes;
- and
- with matrix multiplication circuitry in the integrated circuit, receiving the partial syndromes from the partial syndrome calculation circuitry and generating parity check symbols.
A Reed-Solomon encoder circuit, comprising:
- partial syndrome calculation circuitry that receives a message and that outputs partial syndromes;
- a first set of multipliers that multiplies the partial syndromes by a first set of Lagrangian coefficients to output a first set of products;
- a second set of multipliers that multiplies the partial syndromes by a second set of Lagrangian coefficients to output a second set of products;
- a first set of adders for summing the first set of products to output a first parity check symbol;
- and
- a second set of adders for summing the second set of products to output a second parity check symbol.
Dependencies are inferred from the claim text.