Clock Alignment Scheme for Data Macros of DDR PHY

A slave delay locked loop (“SDLL”) comprising:

• an analog to digital converter (“ADC”) for converting an at least one bias voltage from a master delay locked loop (“MDLL”) to at least one digital signal;
• an adder/subtractor block (“adder/sub block”) for adjusting the at least one digital signal based on at least one control signal;
• a digital to analog converter (“DAC”) for converting the at least one adjusted digital signal to at least one analog signal;
• a voltage to current converter (“V2I”) for converting the at least one analog signal to at least one bias current;
• delay elements for generating phase delayed signals based on the at least one bias current;
• and
• a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

A method for operating a master-slave delay locked loop system, comprising

• generating at least one bias voltage by a master delay locked loop (“MDLL”);
• converting the at least one bias voltage by a slave delay locked loop (“SDLL”) to at least one digital signal, wherein the SDLL comprises:
• an analog to digital converter (“ADC”), an adder/subtractor block (“adder/sub block”), a digital to analog converter (“DAC”), a voltage to current converter (“V2”), delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic;
• adjusting the at least one digital signal based on a control signal by the adder/sub block;
• converting the at least one adjusted digital signal to at least one analog signal by the DAC;
• converting the at least one analog signal to at least one bias current by the V2I;
• generating phase delayed signals based on the at least one bias current by the delay elements;
• determining any phase difference between the phase delayed signals by the phase detector and control logic;
• and
• generating the control signal by the phase detector and control logic, wherein the control signal is inputted to the adder/sub block for aligning the phase delayed signals.