Method and circuitry for controlling a depletion-mode transistor

A method of controlling a depletion-mode transistor, the method comprising:

• in response to absence of a fault condition, turning on a first transistor having:
• a drain coupled to a source of the depletion-mode transistor;
• a source coupled to a first voltage node;
• and a gate coupled to a control node;
• in response to an input node having a first logic state, turning on a second transistor having:
• a drain coupled to a gate of the depletion-mode transistor;
• a source coupled to the first voltage node;
• and a gate coupled through at least one first logic device to the input node;
• in response to the input node having the first logic state, turning off a third transistor having:
• a drain coupled to the gate of the depletion-mode transistor;
• a source coupled to a second voltage node;
• and a gate coupled through at least one second logic device to the input node;
• and
• in response to the input node having a second logic state, turning off the second transistor, and turning on the third transistor.

Circuitry for controlling a depletion-mode transistor, the circuitry comprising:

• a first transistor having:
• a drain coupled to a source of the depletion-mode transistor;
• a source coupled to a first voltage node;
• and a gate coupled to a control node;
• wherein the first transistor is an enhancement-mode NFET;
• a second transistor having:
• a drain coupled to a gate of the depletion-mode transistor;
• a source coupled to the first voltage node;
• and a gate coupled through at least one first logic device to an input node;
• wherein the second transistor is a PFET;
• a third transistor having:
• a drain coupled to the gate of the depletion-mode transistor;
• a source coupled to a second voltage node;
• and a gate coupled through at least one second logic device to the input node;
• wherein the third transistor is an NFET;
• and
• fault detection circuitry adapted to detect a fault condition, wherein the fault detection circuitry is coupled to the control node and is adapted to turn off the first transistor in response to existence of the fault condition, wherein turning off the first transistor is for turning off the depletion-mode transistor, and wherein the fault condition includes at least one of:
• an under-voltage condition;
• an over-voltage condition;
• an over-current condition;
• and an over-temperature condition;
• wherein:
• the at least one first logic device is adapted to turn on the second transistor in response to the input node having a first logic state, and is adapted to turn off the second transistor in response to the input node having a second logic state;
• and the at least one second logic device is adapted to turn off the third transistor in response to the input node having the first logic state, and is adapted to turn on the third transistor in response to the input node having the second logic state;
• and
• wherein:
• the at least one first logic device is coupled to the fault detection circuitry, and is adapted to turn on the second transistor in response to absence of the fault condition, and is adapted to turn off the second transistor in response to existence of the fault condition;
• and the at least one second logic device is coupled to the fault detection circuitry, and is adapted to turn off the third transistor in response to absence of the fault condition, and is adapted to turn on the third transistor in response to existence of the fault condition.