Circuit and method for reducing mismatch for combined clock signal

A circuit comprising:

• a cycle-cycle detector, comprising
• a digital-time converter configured to receive a synthesized clock signal and generate a delayed clock signal according to a tuning signal;
• a first DFF connected to the digital-time converter, and configured to detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal according to the delayed clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals, and the cycle difference index signal indicates difference between two neighboring cycles for the synthesized clock signal;
• a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals;
• and
• a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector;
• wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.