Regulator circuit and semiconductor integrated circuit device

A regulator circuit comprising:

• a first transistor of a first conductivity type configured to reduce an external supply voltage and output an internal active voltage to an output node;
• a first detector configured to receive a criteria level, detect the internal active voltage based on a state of an enable signal, control a gate voltage of the first transistor, and adjust an output current of the first transistor;
• a second transistor of the first conductivity type configured to reduce the external supply voltage, and output an internal standby voltage corresponding to the internal active voltage to the output node;
• a second detector configured to receive a reference voltage, detect the internal standby voltage regardless of the state of the enable signal, control a gate voltage of the second transistor, and adjust an output current of the second transistor;
• and
• a third switch configured to control whether to output the internal standby voltage to the output node, wherein
• the internal standby voltage is input as the standard potential of the first detector.

A semiconductor integrated circuit device comprising:

• a regulator circuit;
• and
• an internal circuit where the voltage of the output node of the regulator circuit is used, wherein the regulator circuit comprises:
• a first transistor of a first conductivity type configured to reduce an external supply voltage and output an internal active voltage to an output node;
• a first detector configured to receive a criteria level, detect the internal active voltage based on a state of an enable signal, control a gate voltage of the first transistor, and adjust an output current of the first transistor;
• a second transistor of the first conductivity type configured to reduce the external supply voltage, and output an internal standby voltage corresponding to the internal active voltage to the output node;
• a second detector configured to receive a reference voltage, detect the internal standby voltage regardless of the state of the enable signal, control a gate voltage of the second transistor, and adjust an output current of the second transistor;
• a first switch configured to control whether to output the reference voltage as the criteria level of the first detector;
• and
• a second switch configured to control whether to output the voltage of the output node as the criteria level of the first detector.