Semiconductor device

A semiconductor device comprising:

• a internal circuit that operates on power supplied by coupling one of two types of power supply terminals, a main power supply terminal which is coupled to a main power supply and a backup power supply terminal which is coupled to a backup power supply, to an internal power supply node,
• wherein switching the coupling between the two terminals is made by a switchover circuit and, in a process of switching to couple one of the two types of power supply terminals to the internal power supply node, the switchover circuit delays decoupling of a power supply terminal to be decoupled later than coupling of a power supply terminal to be coupled and makes a delay,
• wherein the switchover circuit comprises:
• a comparison circuit which compares a supply voltage supplied to the main power supply terminal with a reference voltage;
• a first delay circuit which receives, as an input, an output of the comparison circuit, waits for a first delay time upon the input, and reflects a level change of the input to its output;
• a second delay circuit which receives, as an input, an output of the comparison circuit, waits for a second delay time that is longer than the first delay time upon the input, and reflects a level change of the input to its output;
• a first logical gate circuit which receives, as an input, an output of the comparison circuit and an output of the first delay circuit and generates a first signal to control coupling/decoupling of the main power supply terminal to/from the internal power supply node;
• and
• a second logical gate circuit which receives, as an input, an output of the comparison circuit and an output of the second delay circuit and generates a second signal to control coupling/decoupling of the backup power supply terminal to/from the internal power supply node,
• wherein the switchover circuit comprises:
• a first MOS switch circuit which is placed between the main power supply terminal and the internal power supply node and ON/OFF controlled by the first signal;
• and
• a second MOS switch circuit which is placed between the backup power supply terminal and the internal power supply node and ON/OFF controlled by the second signal,
• wherein a response time for turning the first MOS switch circuit from an ON state to an OFF state circuit is made longer than a response time for turning it from an OFF state to an ON state and a response time for turning the second MOS switch circuit from an ON state to an OFF state is made longer than a response time for turning it from an OFF state to an ON state,
• wherein after the second MOS switch circuit changes in the ON state from the OFF state, the first MOS switch circuit changes in the OFF state from the ON state, and the second MOS switch circuit changes in the OFF state from the ON state after the first MOS switch circuit changes in the ON state from the OFF state.