Circuit board bypass assemblies and components therefor

A chip package bypass assembly, comprising:

• a chip package, the chip package including an integrated circuit supported on a substrate, the substrate including a plurality of contacts disposed on a first surfaces of the substrate, the chip package further including high speed leads extending from high speed data transmission circuits of the integrated circuit to the plurality of contacts disposed at termination areas of the substrate;
• at least one cable containing a first wire pair, the first wire pair including a pair of differential signal conductors extending lengthwise between first and second free ends of the cable, and a drain wire associated with the first wire pair;
• an external connector interface including a conductive housing body having a plurality of walls that cooperatively define a hollow interior space, one of the walls including a bottom wall that extends completely across a bottom of the housing body and which closes off a bottom of the housing body interior space, the housing body further including a front end with an entrance communicating with the interior space;
• a receptacle connector disposed within the housing body interior space, the receptacle connector including an insulative housing and including at least two connector elements therein, each connector element including conductive signal and ground terminals with contact portions for contacting opposing contacts of a mating connector, and tail portions for terminating to the cable, the contact and tail portions extending lengthwise through the connector;
• first free ends of the signal conductors of the first wire pair being directly terminated to corresponding tail portions of the signal terminals of the connector and the drain wire of the first wire pair being terminated to at least one corresponding ground buss of the connector, the first wire pair and drain wire extending through a rear wall of the conductive housing body;
• and,
• second free ends of the signal conductors and drain wire of the first wire pair being connected to the chip package substrate to thereby define a first high speed transmission line extending from the integrated circuit high speed data transmission circuit to the external connector port.

A chip package bypass assembly, comprising:

• a chip package, the chip package including an integrated circuit supported on a substrate, the substrate including a plurality of contacts disposed on opposing first and second surfaces of the substrate, the chip package further including high speed leads extending from high speed data transmission circuits of the integrated circuit to associated first and second contact pads disposed at termination areas supported by the substrate on a surface other than the substrate second surface, and leads other than high speed leads extending from circuits other than the integrated circuit high speed data transmission circuits to contacts supported by the substrate second surface;
• at least one cable containing a first wire pair, the first wire pair including a pair of differential signal conductors extending lengthwise between first and second free ends of the cable, and a drain wire associated with the wire pair;
• an I/O connector including an insulative housing and including at least two connector elements therein, each connector element including conductive signal and ground terminals with contact portions for contacting an opposing connector and tail portions for terminating to the cable, the contact and tail portions extending lengthwise and terminals having equal lengths;
• first free ends of the signal conductors of the first wire pair being directly terminated to corresponding tail portions of the signal terminals of the I/O connector and the drain wire of the first wire pair being terminated to at least one corresponding ground buss of the connector, the first wire pair and drain wire extending through a rear wall of the connector element;
• and,
• second free ends of the signal conductors and drain wire of the first wire pair being terminated to the chip package substrate to thereby define a first high speed transmission line extending from the integrated circuit high speed data transmission circuit to the external connector port.