US 2018/0006158 A1 · FIN-BASED NONVOLATILE MEMORY STRUCTURES, INTEGRATED CIRCUITS WITH SUCH STRUCTURES, AND METHODS FOR FABRICATING SAME

Abstract

Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.

Claims21

Dependent claims

An integrated circuit comprising:

a substrate;
and
a dual-bit nonvolatile memory (NVM) structure overlying the substrate and including:
a primary fin structure, a first adjacent fin structure and a second adjacent fin structure laterally extending in parallel over the substrate, wherein the primary fin structure includes a source region, a channel region, and a drain region, wherein the first adjacent fin structure includes a first program/erase gate, and wherein the second adjacent fin structure includes a second program/erase gate;
a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure;
a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure;
and
a control gate adjacent the primary fin structure.

5 more elements

A nonvolatile memory (NVM) structure comprising:

a primary fin structure having a first side surface and a second side surface;
an adjacent fin structure parallel to the primary fin structure and adjacent the first side surface;
a first junction region and a second junction region in the primary fin structure;
a first channel region at the first side surface between the first junction region and the second junction region;
a third junction region in the adjacent fin structure;
a floating gate adjacent the first channel region, wherein no portion of the floating gate lies directly over the primary fin structure;
and
a control gate adjacent the floating gate.

5 more elements

Dependencies are inferred from the claim text.

Fin-based nonvolatile memory structures, integrated circuits with such structures, and methods for fabricating same

Life of this patent

Fin-based nonvolatile memory structures, integrated circuits with such structures, and methods for fabricating same

Life of this patent

Abstract

Claims21