Semiconductor device including optimized elastic strain buffer

A method of straining in a channel region of a fin-type field effect transistor (finFET), the method comprising:

• forming a strain-inducing, layer on an upper surface of a semiconductor substrate, the strain-inducing layer having a first lattice constant that is mismatched with respect to a second lattice constant of the semiconductor substrate;
• forming an active semiconductor layer on an upper surface of the strain-inducing layer, the active semiconductor layer having a third lattice constant that is mismatched with respect the first lattice constant;
• patterning the active semiconductor layer to form at least one semiconductor fin that defines a channel region of the finFET;
• etching the strain-inducing layer to increase a depth of the at least one fin and relieve a first strain applied to the strain-inducing layer while inducing a second strain applied to the at least one semiconductor fin;
• and
• extending the depth of the at least one semiconductor fin into the semiconductor substrate and below the strain-inducing layer so as to increase the second strain applied to the channel region defined by the semiconductor fin,
• wherein extending the depth includes etching the semiconductor substrate such that a distance extending along the vertical axis between the strain-inducing layer and an upper surface of the semiconductor substrate equals, or is greater than, a thickness of the strain-inducing layer extending along the vertical axis.

A fin-type field effect transistor (finFET) including a strained channel region, the finFET comprising:

• a semiconductor substrate extending along a first axis to define a length, a second axis perpendicular to the first axis to width, and a third axis perpendicular to the first and second axes to define a height;
• at least one semiconductor fin on an upper surface of the semiconductor substrate, the at least one semiconductor fin comprising:
• a semiconductor substrate portion on an upper surface of the semiconductor substrate;
• a strain-inducing portion on an upper surface of the semiconductor substrate portion;
• and
• an active semiconductor portion defining a strained channel region on an upper surface of the strain-inducing portion,
• wherein a first height of the semiconductor substrate portion extending along the third axis is equal, or is greater than, a second height of the strain-inducing portion extending along the third axis.